In general, this invention relates to digital signal processing. More particularly, this invention relates to a technique for identifying the successive words of a serial bit stream digital signal, where the slew rate (rate of change) of successive words within the signal are limited to a predetermined maximum limit so that separate synchronization indicia are not required.
A digital signal generally comprises a serial stream of bits formed from successive words, each word having the same number of bits. In processing the digital signal, it is necessary to make certain that each word is correctly identified, so that the information represented by the word may be recovered and properly utilized. If the sequence of words is not correctly identified, then, incorrect operation of the equipment utilizing the digital signal will result.
Several techniques have been proposed to insure proper identification of successive words in a serial bit stream digital signal. In one such technique, each word in a serial bit stream is separated from its adjacent words by means of a specially coded sequence of bits (e.g., "start" and "stop" bits) constituting sync for the serial bit stream. (See: The Art of Electronics, Horowitz and Hill, Cambridge University Press, Cambridge 1980, page 477.) Typically, about 10% or more of the bits in a serial bit stream containing sync bits are dedicated to the definition of sync. Such a technique is disadvantageous because it increases the complexity of circuitry for identifying successive words of a digital signal and because it results in a reduced utilization of available channel capacity.
Another technique is disclosed in U.S. Pat. No. 4,008,831, issued May 9, 1978, patentee Butcher et al. As disclosed, the characteristic of one of the bits of a byte is modified to indicate the start or end of the byte. A pulse code modulated signal comprising a series of digital pulses is modified so that the position of one of the pulses in a byte serves as synchronizing indicia for the byte. An analogous technique disclosed in U.S. Pat. No. 4,404,676, issued Sept. 13, 1983, patentee DeBenedictis, utilizes a data dependent code word to mark a boundary of a multibyte block of data. The code word also effects error correction of the data block. The techniques disclosed in both of these patents are disadvantageous in requiring complex processing circuitry and in resulting in reduced data rate and/or data capacity
Another relevant technique is disclosed in commonly assigned U.S. Pat. No. 4,493,092, issued Jan. 8, 1985, patentee Veillard. As disclosed, the start and end of words within a bit stream, without the provision of special sync-defining bits, are determined by monitoring the number of times that corresponding bits from successive words switch their states. Like order bits of successive words are compared and counts stored of bit changes. A sync pulse is produced when a predetermined threshold count is reached. Although the disclosed technique may be useful for its intended purpose, the circuit required is expensive and complex in the use of several storage registers and logic components.